The present invention relates to a semiconductor device of multilayer structure, and particularly to a semiconductor device including fine conductive lead circuit layer. Further the present invention relates to a method for manufacturing the semiconductor device.
Heretofore a conventional semiconductor device of multilayer structure has had a circuit structure somewhat as shown in FIGS. 1 (a) and (b). The semiconductor device comprises a silicon substrate 1, a silicon oxide layer 2, a first aluminum lead circuit layer 3, a silicon oxide layer 4 and a second aluminum lead circuit layer 7.
The silicon oxide layer 2 is layered on the silicon substrate 1. The first aluminum lead circuit layers 3 are provided on the silicon oxide layer 2. The silicon oxide layer 4 having plural holes 8 is provided over the first aluminum lead circuit layer 3 and the silicon oxide layer 2 by depositing silicon oxide on the first aluminum lead circuit layer 3 and the silicon oxide layer 2 by the bias ECR (Electron Cyclotron Resonance) plasma CVD (Chemical Vapor Deposition), forming a photo resist pattern on the formed silicon oxide layer and anisotropically etching the holes 8. The upper aluminum lead circuit layer 7 is provided on the silicon oxide dielectric layer 4 having the holes 8.
In the above-mentioned conventional semiconductor device, a line width of the first aluminum lead circuit layer 3 is partially widened at a connection portion thereof with the second aluminum lead circuit layer 7. For this reason, if a width of the lower aluminum lead circuit layer 3 is 1.0 .mu.m, a distance between the first aluminum lead circuit layers 3 is 1.0 .mu.m, an area of the holes 8 is 1.0 .mu.m.sup..quadrature., and allowance of the holes 8 against the adjacent first aluminum circuit layer 3 is 0.5 .mu.m, the pitch of the first aluminum lead circuit layers 3 becomes 2.5 .mu.m.
As above-mentioned, in the conventional semiconductor device, in order to prevent the holes 8 from locating outside the connection portion of the lower aluminum lead circuit layer 3, a line width of the lower aluminum lead circuit layer 3 is partially widened at the connection portion of the lower aluminum lead circuit layer 3 with the upper aluminum lead circuit layer 7. Therefore a pitch between the lower aluminum lead circuit layer 3 having, the connection portion thereof with the upper aluminum lead circuit layer and the adjacent lower aluminum lead circuit layer 3 not having it is increased as compared with a pitch between the two lower aluminum lead circuit layers each not having the connection portion thereof with the upper aluminum lead circuit layer, which hinders the semiconductor integrated circuit from being formed with high layout density.